N1005 IBM Research: photonics

IBM Scientists Present III-V Epitaxy and Integration to Go Below 14nm

<div class="BodyA"><span style="font-size: small;"><span style="font-family: Arial,Helvetica,sans-serif;">IBM scientists in Zurich and Yorktown Heights, New York have unveiled a breakthrough approach in two publications for growing and integrating nano-sized III-V semiconductor devices on silicon. Both papers offer the microelectronics industry a possible answer to the long term challenge of creating a new powerful and energy efficient, yet smaller transistor to pave path for technology scaling for advanced CMOS nodes. </span></span></div><div class="BodyA"><span style="font-size: small;"><span style="font-family: Arial,Helvetica,sans-serif;"><br /></span></span></div><div class="BodyA"><span style="font-size: small;"><span style="font-family: Arial,Helvetica,sans-serif;">Researchers from the <a href="http://www.zurich.ibm.com/st/nanoscale/">I</a><a href="http://www.zurich.ibm.com/st/nanoscale/">BM</a><a href="http://www.zurich.ibm.com/st/nanoscale/">’</a><a href="http://www.zurich.ibm.com/st/nanoscale/">s Materials Integration and Nanoscale Devices</a> group demonstrated a novel, robust and yet versatile approach for integrating III-V compound semiconductor crystals on silicon wafers – a novel and an important step toward making chips smaller and more powerful at lower power density.</span></span><br /><a name="more"></a></div><table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody><tr><td style="text-align: center;"><span style="font-size: small;"><span style="font-family: Arial,Helvetica,sans-serif;"><a href="http://www.aip.org/sites/default/files/aippub/journal-highlights/images/APL-Schmid-IBM-resized.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="175" src="http://www.aip.org/sites/default/files/aippub/journal-highlights/images/APL-Schmid-IBM-resized.jpg" width="400" /></a></span></span></td></tr><tr><td class="tr-caption" style="text-align: center;"><span style="font-family: Arial,Helvetica,sans-serif; font-size: x-small;"><span class="caption none" style="width: 820px;">Scanning electron  microscope images of single crystal structures fabricated<br />using template-assisted selective epitaxy. For better visibility, the silicon<br />is colored in green, and the compound semiconductor in red.</span></span></td></tr></tbody></table><div class="BodyA"><span style="font-size: small;"><span style="font-family: Arial,Helvetica,sans-serif;">The technique developed can be used to combine III-V materials, including indium, gallium and arsenide (InGaAs), with silicon germanium technology to create CMOS chips. It is fully compatible with current high volume chip fabrication technology, making it economically viable for chip manufacturers.</span></span> </div><div class="BodyA"><span style="font-size: small;"><span style="font-family: Arial,Helvetica,sans-serif;"><br /></span></span></div><div class="BodyA"><span style="font-size: small;"><span style="font-family: Arial,Helvetica,sans-serif;">The first paper was published last week in the journal <a href="http://www.aip.org/publishing/journal-highlights/futuristic-components-silicon-chips-fabricated-successfully">Applied Physics Letters</a> <span class="MsoCommentReference"><span style="color: windowtext;"><a class="msocomanchor" href="https://www.blogger.com/blogger.g?blogID=3821464279005499761#_msocom_1" id="_anchor_1" name="_msoanchor_1"></a></span></span>by lead author Heinz Schmid who describes the crystal growth starting from a small area and evolving into a much larger, defect-free crystal. In this so-called template-assisted selective epitaxy the oxide templates are defined and selectively filled via epitaxy to create arbitrary shaped III-V semiconductors such as nanowires, cross junctions, nanostructures containing constrictions and 3D stacked nanowires. </span></span></div><div class="BodyA"><span style="font-size: small;"><span style="font-family: Arial,Helvetica,sans-serif;"><br /></span></span></div><div class="BodyA"><span style="font-size: small;"><span style="font-family: Arial,Helvetica,sans-serif;">Using this small seed area epitaxy, today at the <span lang="DE"><a href="http://www.vlsisymposium.org/press_kit.html"><span class="Hyperlink0">VLSI Symposium</span></a></span> in Kyoto, IBM scientist <a href="https://www.linkedin.com/pub/lukas-czornomaz/2b/340/715">Lukas Czornomaz</a> is <a href="http://www.vlsisymposium.org/images/press_kit/tec/T-178.pdf">presenting</a> a solution for large scale and controlled integration of high quality InGaAs on bulk Silcon (Si) which is based on standard CMOS process modules. Gate-first CMOS-compatible InGaAs FinFETs on Si with excellent performance have been demonstrated and integrated seamlessly in a CMOS manufacturing flow. </span></span></div><table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody><tr><td style="text-align: center;"><span style="font-size: small;"><span style="font-family: Arial,Helvetica,sans-serif;"><a href="https://farm6.staticflickr.com/5336/18638973940_6e438df123_c.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="205" src="https://farm6.staticflickr.com/5336/18638973940_6e438df123_c.jpg" width="400" /></a></span></span></td></tr><tr><td class="tr-caption" style="text-align: center;"><span style="font-family: Arial,Helvetica,sans-serif; font-size: x-small;">Cross-sectional TEM view along InP integrated on Si using the new technique.<br />High number of defects are observed at the seed region by<br />HR-STEM(b)/TEM(c) mostly consisting of stacking faults. Away from the seed,<br />a perfect lattice structure is observed with 8% mismatch to Si corresponding to fully relaxed InP (d,e).</span></td></tr></tbody></table><div class="BodyA"><span style="font-size: small;"><span style="font-family: Arial,Helvetica,sans-serif;">Integrating high quality III-V materials on silicon is critical for getting the benefit of higher electron mobility to build transistors with improved power and performance for technology scaling at 7 nm and beyond. Unfortunately, growing III-V materials on 300 mm silicon substrates isn’t easy and often produces wafers with so many defects that they are rendered useless. </span></span> </div><div class="BodyA"><span style="font-size: small;"><span style="font-family: Arial,Helvetica,sans-serif;"><br /></span></span></div><div class="BodyA"><span style="font-size: small;"><span style="font-family: Arial,Helvetica,sans-serif;">The described novel epitaxy and integration process allows the materials to be grown precisely with a low number of defects on the wafer position where they are needed and therefore represent a significant, economical and manufacturable breakthrough towards the introduction of high-mobility channels into advanced CMOS nodes. </span></span></div><span style="font-size: small;"><span style="font-family: Arial,Helvetica,sans-serif;"><br /></span></span><span style="font-size: normal;"><span style="font-family: Arial,Helvetica,sans-serif;">The new technique may also impact photonics on silicon, with active photonic components integrated seamlessly with electronics for greater functionality.<span style="border: medium none; color: black;"> </span></span></span><br /><br /><span style="font-size: normal;"><span style="font-family: Arial,Helvetica,sans-serif;">Both papers are part of <a href="https://www-03.ibm.com/press/us/en/pressrelease/44357.wss">IBM’s $3 billion</a>, five year investment to push the limits of silicon technology to 7 nanometers and below. More specifically, IBM scientists are motivated to integrate III-V materials on silicon for faster and more powerful devices. IBM is betting that future chips made of these materials will create more energy efficient and powerful cloud data centers and consumer devices.</span></span>

finFET III-V nano photonics silicon transistor IBM Scientists Present III-V Epitaxy and Integration to Go Below 14nm

IBM scientists in Zurich and Yorktown Heights, New York have unveiled a breakthrough approach in two publications for growing and integratin...

Silicon photonics: The future of high-speed data

9:22 AM N1000 0

<div class="MsoNormal"><i>Editor's note: This article is by Dr. Will Green, Silicon Integrated Nanophotonics  department manager, IBM Research</i></div><div class="MsoNormal"><br /></div><div class="separator" style="clear: both; text-align: center;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg5n0NgPo6LYe2maDYd1z0T3NDvNC8tgaoMfguZt_Xfefykf76WVyG9rOqRmgKbIwN6AYknJr5me84olayeIVOWr1p9OQWqkjhORGleMcPEyNt16AZ6lVdNJGUswgBqKdx8HRlUoOjxWoI/s1600/willl+green.jpg" imageanchor="1" style="clear: left; float: left; margin-bottom: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg5n0NgPo6LYe2maDYd1z0T3NDvNC8tgaoMfguZt_Xfefykf76WVyG9rOqRmgKbIwN6AYknJr5me84olayeIVOWr1p9OQWqkjhORGleMcPEyNt16AZ6lVdNJGUswgBqKdx8HRlUoOjxWoI/s1600/willl+green.jpg" /></a></div><div class="MsoNormal">IBM’s research in <a href="http://asmarterplanet.com/blog/2014/08/introducing-brain-like-chip-revolutionize-computing.html" target="_blank">brain-inspired computing</a>, <a href="http://asmarterplanet.com/blog/2015/04/golden-era-quantum-computing.html" target="_blank">quantum computing</a>, and silicon photonics is preparing to take computing in entirely new directions. The neuromorphic chip is getting smarter, the quantum bits are being scaled out, and in the near future, my team’s <a href="http://asmarterplanet.com/blog/2015/05/major-advance-light-silicon-meet.html" target="_blank">CMOS Integrated Nano-Photonics Technology</a> will help ease data traffic jams in all sorts of computing and communications systems – pushing cloud computing and Big Data analytics to achieve their full potential.</div><div class="MsoNormal"><br /></div><div class="MsoNormal">For the first time, we have designed and tested a fully integrated, wavelength-multiplexed silicon photonics chip capable of optically transmitting and receiving information at data rates up to 25 Gb/s per channel. This will soon make it possible to manufacture optical transceivers capable of transmitting 100 gigabits of data per second.<br /><a name="more"></a></div><div class="MsoNormal"><br /></div><div class="MsoNormal">Silicon photonics technology gives computational systems the ability to use pulses of light to move data at high speeds over optical fibers, instead of using conventional electrical signals over copper wires. Optical interconnects, based on <a href="http://en.wikipedia.org/wiki/Vertical-cavity_surface-emitting_laser" target="_blank">vertical-cavity surface-emitting laser (VCSEL)</a> technology and multi-mode fiber, are already being used in systems today. But their transmission range is limited to a relatively short distance of about 150 meters. Today, large data centers continue to scale in size to support exponentially growing traffic from social media, video streaming, cloud storage, sensor data, and much more. The longest optical links in such systems can be more than a kilometer in length. As a result, new optical interconnect solutions that can meet these requirements at low cost are needed to keep up with future system growth.<br /><br /><span style="font-size: large;"><b>How light boosts bandwidth </b></span></div><div class="MsoNormal"><br /></div><div class="MsoNormal">Our silicon photonics technology is designed to transmit optical signals via single-mode optical fibers, which can support links many tens of kilometers long. Moreover, we have built in the capability to use multiple colors of light, all multiplexed to travel within the same optical fiber, to boost the total data capacity carried. The recently demonstrated silicon photonic chip can combine four wavelengths (all within the telecommunications infrared spectrum), allowing us to transmit four times as much data per fiber. The chip demonstrates transmission and reception of high-speed data at 25 Gb/s over each of these four channels, so within a fully multiplexed design, we’re able to provide 100 Gb/s aggregate bandwidth.</div><div class="MsoNormal"><br /></div><table align="right" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: right;"><tbody><tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjVklPK51TPyKWGQdHfbz9WKukVaceR62AUux1WSLX2A5H-05uxP8QJ9irHxQmDTmPv0_whWg-F0lNkgi_0WXLu-AkNF791cOqs0Mo3tdRfEcGZOx5jK-BImmAsT7yoBpO2j2WCSiiNgCA/s1600/silicon+photonics+casette.jpg" imageanchor="1" style="clear: right; margin-bottom: 1em; margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjVklPK51TPyKWGQdHfbz9WKukVaceR62AUux1WSLX2A5H-05uxP8QJ9irHxQmDTmPv0_whWg-F0lNkgi_0WXLu-AkNF791cOqs0Mo3tdRfEcGZOx5jK-BImmAsT7yoBpO2j2WCSiiNgCA/s1600/silicon+photonics+casette.jpg" /></a></td></tr><tr><td class="tr-caption" style="text-align: center;">A cassette carrying several hundred chips<br />intended for 100 Gb/s transceivers,<br />diced from wafers fabricated with<br />IBM CMOS Integrated<br />Nano-Photonics Technology</td></tr></tbody></table><div class="MsoNormal">In addition to the expanded range and bandwidth per fiber, our new photonics technology holds several other advantages over what is available today. Perhaps most importantly, the technology’s manufacturing makes use of conventional silicon microelectronics foundry processes, meaning volume production at low cost. In addition, the entire chip design flow, including simulation, layout, and verification, is enabled by a hardware-verified process design kit, using industry-standard tools. As a result, a high-speed interconnect circuit designer does not require an in-depth knowledge of photonics to build advanced chips with this technology. They can simply follow the standard practices already in place in the CMOS industry. </div><div class="MsoNormal"><br /></div><div class="MsoNormal">This unified design environment is mirrored by our integrated platform, which allows us to fabricate both the electronic and photonic circuit components on a single silicon chip. Rather than breaking up the electrical and optical functions, we integrated the optical components side by side with sub-100nm CMOS electrical devices. This results in a smaller number of components required to build a transceiver module, as well as a simplified testing and assembly protocol, factors which further contribute to substantial cost reductions. </div><div class="MsoNormal"><br /></div><table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody><tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhlwCXret0i3c51WQemKs_dSMPRULG7rOlRm2r5tnRhIVA8iMAlr1mZ0vxPHs0-mDuQuQSEBhGWMNSG2SZlHPeNG9cf7DH2mF9Hh2jBf2qZWvaG3VOh9uLxNHGwtqWB1SOavezPNrjMxbw/s1600/silicon+photonics+packing+structure+medium.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="249" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhlwCXret0i3c51WQemKs_dSMPRULG7rOlRm2r5tnRhIVA8iMAlr1mZ0vxPHs0-mDuQuQSEBhGWMNSG2SZlHPeNG9cf7DH2mF9Hh2jBf2qZWvaG3VOh9uLxNHGwtqWB1SOavezPNrjMxbw/s400/silicon+photonics+packing+structure+medium.jpg" width="400" /></a></td></tr><tr><td class="tr-caption" style="text-align: center;">Performance of the fully integrated, wavelength-multiplexed silicon photonics <br />technology demonstrator chip. The eye diagrams illustrate four separate <br />transmitter channels (right) exchanging high-speed data with four receiver <br />channels (left), each running at a rate of 25 Gb/s.</td></tr></tbody></table><div class="separator" style="clear: both; text-align: center;"></div><div class="MsoNormal">While the primary applications for silicon photonics lie within the data center market, driven by Big Data and cloud applications, this technology is also poised to have a large impact within mobile computing. There’s a need for low-cost optical transceivers to shuttle large volumes of data between wireless cellular antennae and their base stations, often located many kilometers away. As the data bandwidth available to mobile users increases generation after generation, the number of individual cells required to support the traffic does the same. Our technology can deliver faster data transfer in higher volume and across larger areas, in order to support the inevitable growth while controlling costs.</div><div class="MsoNormal"><br /></div><div class="MsoNormal">There has been significant discussion around the 50<sup>th</sup>anniversary of <a href="http://asmarterplanet.com/blog/2015/04/end-moores-law-search-next-switch.html" target="_blank">Moore’s Law</a> and about whether it has reached its end. Silicon photonics fits into that "next switch" conversation. On the processor side, there’s still a fairly consistent trajectory in terms of CMOS technology scaling – down to 10nm, 7nm, and even smaller. The role of our CMOS Integrated Nano-Photonics technology will be to reduce communication bottlenecks inside of systems, and to allow expansion of their capacity for processing huge volumes of data in real time.<br /><br />Kilometer-scale data centers are emerging. Big Data and the Internet of Things are connecting people and information in ways that were unimaginable only a few years ago. IBM’s silico<a href="https://www.blogger.com/null" name="_GoBack"></a>n photonics technology will augment that growth on the ground, into the Cloud, and beyond.</div>